(VLSI-SoC 2025) 2025 IFIP/IEEE International Conference on Very Large Scale Integration
Engineering
Conference Date
Oct 12-Oct 15, 2025
Place
Puerto Varas, Chile
Submission Deadline
Apr 18, 2025
E-mail
victor.grimblatt@synopsys.com
The VLSI-SoC Conference, the premier assembly in the realm of Very Large-Scale Integration Systems-on-Chip, is gearing up for its 2025 edition in the stunning natural setting of Puerto Varas, Chile. Esteemed as a pivotal gathering, this conference brings together the brightest minds, pioneers, and visionaries to share groundbreaking research, innovative concepts, and the exploration of current trends in VLSI and SoC technology. Organized by Universidad de La Frontera, this conference isn’t merely an event; it serves as the cornerstone of a comprehensive agenda, hosting specialized workshops, interactive sessions, and a dynamic environment encouraging the exchange of invaluable insights. Join us in the exotic locale of Tangier for an immersive experience at the forefront of modern VLSI and SoC technology.
This 33rd edition of VLSI-SoC will take place in Puerto Varas, a city in Chile’s Lake District about 1,000km south from Santiago (1:45hr by flight). It sits on the southwest banks of the expansive Lake Llanquihue, which offers commanding views of snow-capped Osorno Volcano and Calbuco Volcano, both still active. The city also known as “the city of roses” is famous for its German traditions and a truly stunning natural setting. It enjoys a scenic location close to mountains, lakes, forests, and national parks. Puerto Varas is the southernmost of a string of towns on the western shore of the lake that includes Frutillar and its famous Teatro del Lago a magnificent lakeside concert hall which plays host to top international orchestras and artists.
VLSI-SoC'25 seeks original, unpublished contributions of the following topics of interest
include but are not limited to:
Analog and Mixed-Signal IC Design
3-D Integration
Physical Design
Electronic Design Automation
Variability, Reliability, Fault Tolerance and Test
Digital Signal Processing and Image Processing SoC Design
Prototyping, Validation, Verification, Modelling, and Simulation
Embedded Systems and Processors, Hardware/Software Codesign
Processor Architectures and Multicore SOCs
Logic and High-Level Synthesis
Low-Power and Thermal-aware Design
Reconfigurable SoC Systems for Energy and Reliability
Green Computing Systems
Circuits and Systems for Micro-sensing Applications
Papers should present original research and industrial results not published or submitted for publication in other forums. Electronic submission in PDF format is expected via EasyChair platform for VLSI-SoC 2025. Manuscripts should not exceed 4 pages + a 5th page with only references (single-spaced, 2 columns, 10pt font). Submissions should be in camera-ready, following the IEEE proceedings specifications. The proceedings will be published by IEEE and will be made available through IEEE Xplore. A selection of the conference’s best papers will be invited to submit an extended version to be included as chapters of a book to be published by Springer.
Paper Publication and Presenter Registration:
Papers will be accepted for regular or poster presentation at the conference. Every accept ed paper MUST have at least one author registered at the conference by the time the camera-ready paper is submitted; the author is also expected to attend the conference and present the paper. A limited number of travel grants are available to needy PhD students.